Subject: Using iff example
From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Mon Dec 10 2001 - 20:46:09 PST
Peter,
If I understood our conversation today correctly, the following two
examples are a more correct way to use 'iff':
always @(posedge clock iff load == 1) //synchronous reset
if (!reset) count <= 0;
else if (load) count <= d; //gated input
else count <= count + 1;
always @(posedge clock iff load == 1 or negedge reset) //asynchronous reset
if (!reset) count <= 0;
else if (load) count <= d; //gated input
else count <= count + 1;
But, I still have doubts that this will work correctly. A real counter
should reset regardless of the value of the load input. Section 8.10 says
'iff' has precedence over 'or', so the control input will also disable the
ability to reset the counter.
It seems to me that the only value of 'iff' is at a level of abstraction
where there is no reset logic. This would require synthesis to infer reset
from thin air. It also means there is no way to put simulation into a
known state. I can only see the latter working for 2-state logic in a
design that does not need flip-flops to be set instead of reset.
Can you please enlighten me as to why some of your customers want 'iff'?
Stu
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
This archive was generated by hypermail 2b28 : Mon Dec 10 2001 - 20:44:54 PST