Subject: Re: Using iff example
From: Adam Krolnik (krolnik@lsil.com)
Date: Tue Dec 11 2001 - 08:05:24 PST
Good morning all;
This example also places the reset input conditional on the
load input. E.g. load=0, reset=0, count doesn't change.
always @(posedge clock iff load == 1) //synchronous reset
if (!reset) count <= 0;
else if (load) count <= d; //gated input
else count <= count + 1;
This feature seems to mostly be a small simplification
for verification code.
always @(posedge clk iff the_magic_condition_occurrs)
begin
start_monitoring_something;
...
Of the register library we use on the project, only this one
would benefit from iff - an enabled FF without reset/set.
always @(posedge clk) if (e) q <= d ; // verilog
always @(posedge clk iff e) q <= d ; // verilog++
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
This archive was generated by hypermail 2b28 : Tue Dec 11 2001 - 08:06:02 PST