Subject: Re: Using iff example
From: Michael McNamara (mac@verisity.com)
Date: Tue Dec 11 2001 - 08:32:28 PST
> always @(posedge clock iff load == 1) //synchronous reset
> if (!reset) count <= 0;
> else if (load) count <= d; //gated input
> else count <= count + 1;
>
OK, maybe you all see the emperor's clothes, but I have to ask: why
are we testing load in the behavioral section in the example code?
I mean to my simple mind (and I haven't read the documentation on
this, so am approaching it exactly as would a design familiar with
Verilog 2001), for the simulator to allow one to pass the statement
'always @(posedge clock iff load == 1)'
load must truly be equal to one, right?
_________________
load _____
clock ____/
^
|
Then as in SystemVerilog one cannot interleave execution of other
blocks of code, by the time we check reset, load will still be equal
to one, so we will _ALWAYS_ do the 'count <= d;' block, and never do
the 'count <= count + 1;' block.
>
> This feature seems to mostly be a small simplification
> for verification code.
>
> always @(posedge clk iff the_magic_condition_occurrs)
> begin
> start_monitoring_something;
> ...
>
> Of the register library we use on the project, only this one
> would benefit from iff - an enabled FF without reset/set.
>
> always @(posedge clk) if (e) q <= d ; // verilog
>
> always @(posedge clk iff e) q <= d ; // verilog++
>
>
>
> Adam Krolnik
> Verification Mgr.
> LSI Logic Corp.
> Plano TX. 75074
>
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