Subject: Re: Using iff example - very bad coding style!
From: Alec Stanculescu (alec@fintronic.com)
Date: Tue Dec 11 2001 - 13:29:33 PST
Cliff,
First of all I want to say that you are right in that the original
examples are not working. Your first remark: "On a posedge clk with no
load signal, nothing happens, but both should count" was correct, as
well as your second remark made on the bug inherited by me from the
original description (which had the same problem):"if load == 0, the
second always block will not permit synchronous resets to occur".
So, here is my corrected version for synchronous reset:
always @(posedge clock iff (load == 0) and (reset == 1))
count <= count +1;
always @(posedge clock iff (load == 1) or (reset == 0)) //synchronous reset
if (!reset) count <= 0;
else if (load) count <= d; //gated input
Now, let us talk about race conditions. In case a register is
written from two different processes, there could be a race condition
only in case the two processes attempt to write into the register
simultaneously, and the register could have either value as a result,
depending on which process writes last. However, in this case the
conditions for writing to count are mutual exclusive and therefore no
race condition can occur.
Of course, your training classes address the usage of existing tools
and there you are the expert (I have no idea what Synopsis generates
when it sees multiple processes writing to the same register :-)
So, we may mearge the two processes, as follows:
always @(posedge clock) //synchronous reset
if (!reset) count <= 0;
else if (load) count <= d; //gated input
else count <= count + 1;
Similarly, for the asynchronous reset:
always @(posedge clock iff (load == 0) and (reset == 1))
count <= count +1;
always @(negedge reset) //asynchronous reset
if (!reset) count <= 0;
always @(posedge clock iff (load == 1) and (reset == 1)//gated input
count <= d;
or the mearged version:
always @(posedge clock or negedge reset) //asynchronous reset
if (!reset) count <= 0;
else if (load) count <= d; //gated input
else count <= count + 1;
Alec
> At 09:38 AM 12/11/01 -0800, you wrote:
>
> >Mac,
> >
> >The example should be:
> >
> >always @(posedge clock)
> > if (reset and !load) count <= count + 1;
> >
> >always @(posedge clock iff load == 1) //synchronous reset
> > if (!reset) count <= 0;
> > else count <= d; //gated input
>
> Heavens, No!
>
> Making multiple assignments to the same variable from two different always
> blocks should be highly discouraged (I highly discourage this coding style
> in all of my training classes). This coding style is subject to race
> conditions and is quite confusing, not to mention that if load == 0, the
> second always block will not permit synchronous resets to occur.
>
> >or
> >
> >always @(posedge clock)
> > if (reset and !load) count <= count + 1;
> >
> >always @(posedge clock iff load == 1 or negedge reset) //asynchronous reset
> > if (!reset) count <= 0;
> > else if (load) count <= d; //gated input
>
> Many of the same problems.
>
> >The reason for the check on load here is that reset could have
> >transitioned from 1 to X and load could have been 0.
> >
> >Alec
>
> Synopsys gives warnings about unknown wired logic type, then builds two
> flipflops with outputs anded together. This is really ugly!
>
> Challenge: if anybody thinks they have a model that requires assignments to
> the same variable from more than one always block, send it to me, I will
> re-code it and send it back to you.
>
> Regards - Cliff
>
>
> //*****************************************************************//
> // Cliff Cummings Phone: 503-641-8446 //
> // Sunburst Design, Inc. FAX: 503-641-8486 //
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