Subject: Re: net structs?
From: Peter Flake (flake@co-design.com)
Date: Tue May 07 2002 - 04:51:00 PDT
Paul,
Yes this is the intent. Verilog wires are not the same as VHDL signals
because wires have a built-in resolution function, so cannot be of any
arbitrary data type. In fact they are a special data type with strength
values.
If you want to bundle wires together, use an interface.
Peter.
At 02:26 PM 5/6/02 -0700, Paul Graham wrote:
>Perhaps I'm missing something, but I don't see how to declare a net object
>of a struct type. It appears that nets are restricted to scalars, vectors,
>and packed and unpacked arrays. Is this the intent?
>
>Paul
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