Subject: Re: problem with incomplete type references in draft 8
From: Peter Flake (flake@co-design.com)
Date: Tue May 07 2002 - 04:26:04 PDT
Paul,
There is a long history behind this.
In the original version of SUPERLOG, which was not strictly
Verilog-compatible, you could define a type after using it.
When we changed to being strictly Verilog-compatible we had to withdraw
this feature, and upset some users who had taken advantage of it. The
compromise is to allow an empty typedef, and this conveniently fits with
the ability to define pointers in SUPERLOG, which are not in SystemVerilog
as they are not for design.
BTW complete type checking can only be done during elaboration.
Peter.
At 12:15 PM 5/6/02 -0700, Paul Graham wrote:
>Section 3.5 (User-defined types) says:
>
> A type can be used before it is defined, provided it is first identified
> as a type by an empty typedef:
>
> typedef foo;
> foo f = 1;
> typedef int foo;
>
>Is this really true? Can I do this:
>
> typedef bar;
>
> bar x = { 1'bz, 37 };
>
> typedef struct {
> bit a;
> int b;
> } foo;
>
>In C (and VHDL) you can refer to an incomplete type only to use a pointer to
>that type. The example given in this section suggests that you could do
>something like declare a bunch of incomplete types at the top of a module,
>use them throughout the module, then give their declarations at the end of
>the module, forcing a two-pass compilation. Surely that's not the intent!
>
>On the other hand, since we don't have pointers in the language (yet), why
>allow incomplete types?
>
>Can someone clarify the intent here?
>
>Paul
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