Subject: Re: Proposal for array types
From: Paul Graham (pgraham@cadence.com)
Date: Fri Apr 05 2002 - 09:46:34 PST
Peter,
Thanks for your comments. Here are my comments on your comments:
> The array viewed as a single integer is signed, like Verilog 2001.
> Note that Verilog 2001 defines part selects as unsigned.
I wondered what the meaning of this would be:
reg signed [3:0][3:0] x;
You're suggesting that x[1] is an unsigned quantity. On the other hand, with:
reg signed [3:0] x[3:0]
then x[1] is a signed quantity. Isn't that a bit confusing?
Really, a packed array is like a union of an integer and an array:
union {
signed [15:0] f1;
(unsigned) [3:0] f2 [3:0];
}
In this case, it is clear that f1 is a signed integer, but that the elements
of f2 are unsigned.
Would it not make more sense to use unions like this instead of packed
arrays? Just a thought.
> > [ Also, I see no need to mention 'scalared' and 'vectored' in this
> > section. These keywords have nothing to do with SystemVerilog, and
> > perhaps should be deprecated. In any case, they don't belong in the
> > section on arrays. ]
>
> Where should they be mentioned?
They are mentioned in the LRM-2001 manual. Why should they be mentioned
here? They seem to be useless keywords.
> For any scalar (non-array) type, such as int a; the number of dimensions
> should be 0. The type can be found using $type(a).
What is $type? I didn't find it in draft 5.
Paul
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