Subject: Unconnected inputs
From: Michael McNamara (mac@verisity.com)
Date: Mon Mar 25 2002 - 11:06:53 PST
Given:
module uncon_input(a,b,c) ;
input a;
input [7:0] b;
inout [7:0] c;
initial begin
#10 $display ("A is %b B is %b C is %b", a,b,c);
end
endmodule // uncon_input
Verilog-XL gives me:
Highest level modules:
uncon_input
A is z B is zzzzzzzz C is zzzzzzzz
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.2 secs to compile + 0.0 secs to link + 0.1 secs in simulation
End of VERILOG-XL 3.10.s010 Mar 25, 2002 11:06:35
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