Subject: Verilog++ 6th committee meeting
From: Simon J. Davidmann (simond@co-design.com)
Date: Mon Aug 27 2001 - 11:13:57 PDT
Verilog++ 6th committee meeting - Simon as minute taker.
August 27th, 2001
Attendees
(aaaaaa) Vassilios Gerousis *
(r-aaaa) Dave Kelf * (Peter Flake)
(--aaaa) John Sanguinetti
(a-aaa-) John Emmitt *
(-aa---) Dennis Brophy
(aaaaaa) Stu Sutherland *
(-aaaaa) David Knapp
(ar-aaa) Tom Fitzpatrick *
(aaaaa-) Phil Moorby *
(aaaaaa) Anders Nordstrom *
(aaaaaa) Cliff Cummings *
(aaaaaa) Simon Davidmann *
(aaaa--) Harry Foster *
(-a-aaa) Stefen Boyd
(aaaaaa) David Smith *
(a--aa-) Mike McNamara *
Attendance record key
a = attended, r = representative sent, - = not present
* beside name means attended this meeting - to make it more obvious
Agenda
1) goal is to review to sections as per schedule
>1- Pages 51 - 60
> a- Interfaces.
> b- Parameters.
2) press release
3) assertion requirements
ESS Review: 51-66
SS = Stu Sutherland
PF = Peter Flake - please send updates to whole committee.
SS: p52 last line - processes and continous assignments can be synthesized
but user needs to check how tools use these languages and to see the
restrictions
SS: p53 needs in syntax box syntax ofr interface instance (copy from
appendix p74)
PF p53 - need modport discussed more - to explain what it really is. and
why the two examples do have different. ie "master and slave are declared
as modports because..." needs more discussion on the rationale of modports
(more than just what they are - why they are needed).
PF p57 middle of page "expanded at the port.", need to add something like
move module systemwires middle p57 and put it right about switch wires.
need to add some form of text box?
PF p59 provide task examples of light controller - send to entire team.
and all examples should be called switch and light, eg numbered switch2,
etc.
PF - interface port connections follow same rules as module port
connnections - Peter to find where to put text to this affect to and write
the text.
PF - The issue of 'const' has not been fully discussed, eg having a const
logic passed into an input port - maybe need multiple const's connected -
need to add to port connections rules somewhere - in the modules- and the
interface chapter could reference it.
PF - when done, send whole chapter to Tom Fitzpatrick (Co-Design) to add to
the chapter and add what is needed to make this much better described
(Tom have a look at SystemC 2.0 spec and discussion in interfaces)
NEXT - must review Interfaces again when section re-written
SS: P61 - 3rd line - comment "type of j is type of parameter at elaboration
time"
PF: P60 - needs syntax and explanation of parameter instancing, including
'type'
SS: P64 does not require separate file as they can be declared in the $root.
SS P66 lose everything but new things: `` and `" and `include `f1
SS maybe need to delete pages P62-P66 - await discussion generate...
remember to put section on elaboration back library map information
NEXT TIME
----------------
next time start on page 67
Question on implicit types
--------------------------------------
does there need there to be the ability to have implicit nets extended to
other data types
do we need implicit variables? - but they need to be hierarchically
defined, eg some blocks undefined things could need to be wires, some times
reals, etc
Peter Flake - did think about it - but problem is that he feels that it
breaks existing verilog (in some cases)
Mike McNamara - suggests leave implicit nets alone, and if needed add
something new? - best to leave it into the schematic tool...
Cliff Cummings will send out his paper on this
Peter Flake - we could have "infer type" to be added to the
`default_nettype directive or something better - talk with David Smith and
then come up with some proposal.
Other Issues
-------------------
Cliff Cummings - to look at what the issue is with generate statement to do
with passing in parameter - will send us all a note on this
SS: - need to be able to generate the ports of a module?? is a requirement
- will try and find out what the real requirement is
could generate loop create port lists. it is anomalous that port lists
cannot be in the generate loop.
PF - to think on these
PRESS RELEASE
---------------------------
the board wants to issue a press release about the evolution of verilog and
the verilog++ committee - in time for the F2B conference
it is important that the committee support this (and it is ok if not
mentioning company names)
Dave Kelf will discuss individually with people what they are prepared to say.
ASSERTIONS
---------------------
there will be new language features that will come from the other HDL+
committee based on the requirements that Harry Foster has sent out - so
please do read the assertions requirements as we will have a discussion at
our 24th sept meeting.
FUTURE MEETINGS - phone 7th meeting
-------------------------------
Sep 10th, 2001
Wrap up meeting. Here we can review anything left over and catch up on
tricky items.
We also mentioned that we will look at deprecated items in the meeting.
FUTURE MEETING - F2B
--------------------------------------
there will be face to face Monday 24th Sept in San Jose
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