Subject: RE: SystemVerilog: always_comb and functions
From: Kevin Cameron x3251 (dkc@galaxy.nsc.com)
Date: Thu Mar 28 2002 - 15:08:13 PST
> From owner-vlog-pp@eda.org Thu Mar 28 14:42:31 2002
>
> Hi Kevin,
>
> I'm not sure I see where your comment
>
> > Argh... more stuff working against modular compilation... :-/
>
> applies. You're not suggesting that functions should be compiled in the
> absence of their declaring module, are you? If the smallest unit of compile
> is a module (or interface), then I fail to see how this feature affects
> modular compilation. Please help me understand your concern.
>
> Thanks,
> -Tom
SystemVerilog allows functions standalone (in $root), rather than just in modules
or interfaces, so it seems reasonable to me that you would want to be able to
build libraries as you do with C and C++. A requirement that you can see the
internals of a function stops you just prototyping the function and compiling it
elsewhere. Personnally I'm bored of watching VCS & Debussy reparse/recompile
the entire source every time I make a one-line change.
On the original topic, what would be the rules be for PLI calls rather than native
Verilog function calls?
Kev.
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