FW: Verilog++ Assertion Requirements Proposal

Subject: FW: Verilog++ Assertion Requirements Proposal
From: Vassilios.Gerousis@Infineon.Com
Date: Mon Aug 13 2001 - 08:36:39 PDT

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Hi Verilog++ and assertion committee,
        I am forwarding this document from Harry Foster. This is will be the requirement for adding assertions to the Verilog++ extensions. We will consider this in our next meeting two weeks from today. Give Harry and the committee a feedback. We will spend 20 minutes in our next meeting on August 27.

Thanks for your attention
Vassilios

-----Original Message-----
From: Harry Foster [mailto:foster@rsn.hp.com]
Sent: Wednesday, August 08, 2001 4:24 AM
To: Vassilios.Gerousis@infineon.com
Subject: Verilog++ Assertion Requirements Proposal

Hi Vassilios,

Attached is a preliminary copy of a strawman
proposal I plan to make to the Assertion
committee for Verilog assertion extension
requirements. There is still additional
work required on this document. However,
I wanted a starting point for the committee
to consider to boost our productivity.

Best regards,

-Harry

• application/pdf attachment: AssReq_.pdf

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