Subject: Verilog++ 5th committee meeting - minutes - August 13th, 2001
From: Simon J. Davidmann (simond@co-design.com)
Date: Mon Aug 13 2001 - 11:17:47 PDT
Verilog++ 5th committee meeting - Simon as minute taker.
August 13th, 2001
Attendees
(aaaaa) Vassilios Gerousis *
(-aaaa) Dave Kelf
(-aaaa) John Sanguinetti
(-aaa-) John Emmitt
(aa---) Dennis Brophy *
(aaaaa) Stu Sutherland *
(aaaaa) David Knapp *
(r-aaa) Tom Fitzpatrick (Peter Flake) *
(aaaa-) Phil Moorby *
(aaaaa) Anders Nordstrom *
(aaaaa) Cliff Cummings *
(aaaaa) Simon Davidmann *
(aaa--) Harry Foster *
(a-aaa) Stefen Boyd *
(aaaaa) David Smith *
(--aa-) Mike McNamara
Attendance record key
a = attended, r = representative sent, - = not present
* beside name means attended this meeting - to make it more obvious
SS - Stu Sutherland action
PF - Peter Flake action
REVIEW OF PAST QUESTIONS WITH PETER FLAKE
SS:
Questions on previous items
page 15 - discussion on part selects and what happens on access (read/write)
array elements or slices that are out of range.
for Verilog - can use X state - but in ESS can't do that - 2 state variables,
so tool must generate warning when it occurs.
SS:
Question on parentheses pages 21 (to 31) in particular - example at top shows
parentheses are needed - but it appears that multiple assignment operators
require multiple parentheses
Table on p24 should say that assignment operator has no association. (ie remove
right assoc from table). for all operators on that line.
and fix note on p21 - to it is really clear - maybe new example too. a = (b =
(c = 5 ) );
on page 24 - question was not dimensionality - it has to do with structure
inits and bit packing.
Peter explained that a struct can be implemented with padding (like C).
logic data type question - if do not declare any data type - what is the
default - it is one bit wire to be Verilog compatible.
[so yes need to declare all the one bit variables that exist in procedural
blocks]
PF to think on default variable type.
You can make procedural assignments or continous assignments to logic - but not
both - tool should error.
|| and && should be removed as vector reduction operators (historical reasons -
and now are not needed).
These should be removed on page 23.
globally change bumb operators to incrementor and decrementor.
REVIEW OF PAGES 32-52
SS: p32 - wording in 2nd paragraph.
SS: p32 - combinatorial or combinational - from now on use combinational
SS: delete pages p33-34-35 - to remove discussions on verilog styles.
P36 - Peter Flake explained rationale for State Machines - state variables,
timing controls, and transition statements.
PF: Need example of async FSM (and suggest where it should go)
PF: and example of synch and asynch resets (and suggest where it should go)
p36 - would like state {S1=32, s2=33, s3=22} S; - ie user control over state
encoding.
PF: - consider this as an enhancement.
PF - example of a transition statement with a begin end block in it
SS: tidy up footnote 4 on p36
p37 - 'default' is needed in transition syntax -
PF to send new syntax.
PF send example of fork/join block working on transition implicit named events
such that shows all transitions have fired.
Can we have randomized initialization of states of state variables.
PF - to think on.
SS: p39 - remove comparision chart
PF - more examples of a hierarchical FSM. - maybe IEEECAD one. send out and
see.
SS p40 remove headings of 'discussion' and 'background'
SS p41 delete last 2 lines from first paragraph 'note that the... a.c'
PF p41 - process - would like method of disabling processes as part of ESS, or
remove 'process' from ESS.
-- see next time if we want to leave process in or take it out.
-- maybe show logic design example not verif code.
SS p41 in continuous assignments - use keyword 'reg' and not word registers...
PF p41 need syntax for process on p41
SS: P43 - is void in the BNF somewhere?
PF p43 - need example of void function declaration.
SS p44 remove synhatx etc of Gates, UDP, primitives etc
SS p45 remove line 'in superlog ess port size checking..."
SS p47 can you have instance of nested module before its declaration -
PF to check and explain and add some words
PF - p48 needs an example and description of event as a port item
SS - p48 - need to explain that reals, structs, etc can be passed through ports
SS - p11 default is not 1 femtosecond - it should be 1 second (to be Verilog
compatible) (await PF next item)
PF - will check what the issue is and get back to us.
PF p50- need a section writing on port mismatches for partially unconnected.
SS p52 change 'activation script' to be 'conceptual top level module'
Meeting ended 11.10 am Calif time.
we will start at Interfaces next time.
Simon.
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