Subject: propose limitation of $root declarations
From: Stefen Boyd (stefen@boyd.com)
Date: Mon Aug 13 2001 - 11:57:13 PDT
I would like to see the removal of some of the stuff
currently allowed outside of the scope of a module
boundary. I am not opposed to the visibility
for nested modules, but because of the
definition of the source deck in verilog, global
signals, tasks, functions, etc. in $root can be placed
anywhere and thus are HARD to find.
Ok, so I've been burned. I lost several hours trying
to find several parts of a superlog verification
environment because there were many pieces scattered
in unlikely locations... almost at random. It was
clear that it had been put together in a hurry, and
that any new signals were simply added to the file
that was open in the editor at the time... in some
of the most non-intuitive locations.
PROPOSAL:
Remove some of the stuff that can be placed into
$root. Remove the following from the
<declaration_or_statement> used by <source_text>
<task_declaration>
<function_declaration>
<interface_instantiation>
<event_declaration>
<net_declaration>
<data_declaration>
<statement>
Granted, this might mean we'll need a <root_declaratoin_or_statement>
but throwing this stuff around in the global space is
more painful to maintain than it's worth. I am open
to allowing task and function declarations, but I really
don't want to get global net, variable, or interface instantiations.
We might want to be able to import a module, to get it's declarations,
tasks, and functions, but then we know what we're getting and
some idea of where to look for the stuff we got... for the poor fool
who comes along later and has to maintain a horrid beast of
the past.
Regards,
Stefen
--------------------
Stefen Boyd Boyd Technology, Inc.
stefen@BoydTechInc.com (408)739-BOYD
www.BoydTechInc.com (408)739-1402 (fax)
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