Subject: RE: Proposed BNF Fix for Verilog-2001 Parameter Errata
From: Jayaram Bhasker (jbhasker@cadence.com)
Date: Fri Apr 12 2002 - 06:26:49 PDT
Cliff:
This is a very tricky issue. You really dont want two versions of verilog standard
out there, one described in 1364-2001 and one in 1364.1-2002 (though I dont mind sales of
1364.1 std going up just because prople want to see the latest Verilog BNF).
I think a reasonable solution is to keep the 1364.1 syntax consistent with the 1364 syntax,
but add a footnote in 1364.1 syntax where there is inconsistency detailing some words such as:
"The Verilog BTF WG has found an errata in the 1364-2001. <then describe the correction>.
The WG is most likely to accept these changes in future versions of the 1364 language."
- bhasker
--J. Bhasker Cadence Design Systems 7535 Windsor Drive, Suite A200, Allentown, PA 18195 (610) 398-6312, (610) 530-7985(fax), jbhasker@cadence.com
-----Original Message----- From: Clifford E. Cummings [mailto:cliffc@sunburst-design.com] Sent: Thursday, April 11, 2002 3:13 PM To: vlog-synth@eda.org; vlog-pp@eda.org; btf@boyd.com Subject: Proposed BNF Fix for Verilog-2001 Parameter Errata
Hi, All -
Proposed BNF Fix for Verilog-2001 Parameter Errata
We (I) made a mistake in the Verilog-2001 BNF concerning the definition of the module_parameter_port_list and vendors are starting to implement these parameter port lists incorrectly. We need to fix this in the Verilog-2001 Standard (issue an errata notice), but we also need to make sure that the errata does not propagate to the IEEE Verilog-Synthesis (1364.1) and SystemVerilog (Accellera) standards to compound the problem.
Attached is a full description of the problem and a proposed fix.
Please read and respond.
Regards - Cliff Cummings
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