Subject: Re: SystemVerilog draft4 - PRELIMINARY
From: Peter Flake (flake@co-design.com)
Date: Fri Mar 01 2002 - 10:22:24 PST
Hi Stu,
Good work. Just a couple of comments:
In section 10.5 "only one iff event control" should read "only one event
control".
In section 10.7 you have correctly removed "port". The explanation of the
example was sent on Dec 10, and is repeated here:
The 'while' loop contains a delay of two clock cycles, from the 'repeat'
statement, and this determines the pipeline throughput.
Each iteration spawns a process which lasts six clock cycles, the latency
of the pipeline. The variable 'processes' keeps a count of the number of
currently active processes. The pipeline flush is not complete until this
count has fallen to zero.
Peter.
At 09:01 PM 2/28/02 -0800, Stuart Sutherland wrote:
>All,
>
>I've attached a PDF file with a PRELIMINARY version of draft 4. The BNF
>is still in progress, and should be complete next week. I will finish
>draft 4 at that time, with the BNF excerpts inserted in the chapters.
>
>I would like to have a "clean" draft for distribution at HDLCon that does
>not have all the strike through text. Please review this preliminary
>draft as quickly as possible, and verify that the strike through text and
>"new" text (in blue) looks correct. If all agree by e-mail vote that the
>changes are correct, I will remove the strike through stuff before the
>final draft 4. The new (blue) text can remain in blue--it won't show up
>in the printed document.
>
>Stu
>
>
>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>Stuart Sutherland Sutherland HDL Inc.
>stuart@sutherland-hdl.com 22805 SW 92nd Place
>phone: 503-692-0898 Tualatin, OR 97062
>www.sutherland-hdl.com
>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
>
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