Subject: An Open Process
From: Vassilios.Gerousis@Infineon.Com
Date: Thu Jun 20 2002 - 07:41:11 PDT
Hello Everyone,
I am sending alot of my times trying to get SystemVerilog 3.1 up
and running. I have sent you slides that outline what I propose to happen.
My chairs and I need should be given few days and we will start the activities.
So please have patience.
1- We will agree on a plan for action with my chairs.
2- Each committee will start meeting and planning.
3- Assigned donations is being prepared in PDF in small sizes so that
we can send each one to the appropriate committee.
a- Synopsys was asked to provide smaller chapters to be sent to designated
committee. By Friday, I will send an electronic version.
b- New additional donations must be discussed with me ASAP.
4- We will resolve the issues as we go on. But please help me instead of putting blocks
in front me. Give an opportunity, and if I am not fair, then scream at me.
5- My chairs have the additional responsibility to outline how we will synchronize SystemVerilog Assertions with Sugar. Harry Foster and Erich Marschner will help
in this matter.
So I ask, pretty please to give me a chance to get this rolling ASAP and getting
most issues resolved instead of increasing it.
Best Regards
Vassilios
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Dr. Vassilios Gerousis Infineon Technologies
DAT CAD, MchB
Telephone: +49-89-234-21342 BalanSt. 73
Fax: +49-89-234-23650 D-81541 Munich
email: Vassilios.Gerousis@infineon.com Germany
Site Map: http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2E;HNR=73
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