Subject: RE: addition for intro of systemverilog3.0 document
From: Simon Davidmann (simond@co-design.com)
Date: Mon Dec 10 2001 - 07:57:08 PST
Hello Vassilios,
Ah - so now I am confused.
What Accellera must do in the Accellera standard is to acknowledge in the
document that it comes from the donation of SUPERLOG ESS - this is how
Accellera gets the ability to publish it - this is stipulated in the
donation agreement.
and so I am surprised at your comment - as I have written below what I
suggested in the last meeting and that it seemed people thought was a good
idea.
lets discuss it later.
and regarding the board approving things - you are correct - they need to
approve the document and by inclusion the comments - and in fact as they
have already approved the press release on the subject the inclusion of my
suggested text should be acceptable and should not raise any eyebrows.
so lets discuss later today, include it, and then work on the technical
stuff of the ESS - as we need to start work on the assertions in the Jan
meeting.
Best Regards,
Simon
At 07:18 AM 12/10/2001, Vassilios.Gerousis@infineon.com wrote:
>Hello Simon,
> As I mentioned in an email, before, this type of acknowledgement
>has not been in our practice. We will need to get The Accellera board to
>approve such a paragraph. We will discuss this at the January Board meeting.
>
> What is normal is to acknowledge the people who participated
>in the committee for the development of the standard. This includes
>the names of ALL individuals. This is what we can include today.
>
>Best Regards
>
>Vassilios
>
>-----Original Message-----
>From: Simon Davidmann [mailto:simond@co-design.com]
>Sent: Monday, December 10, 2001 4:08 PM
>To: stuart@sutherland-hdl.com
>Cc: vlog-pp@eda.org
>Subject: addition for intro of systemverilog3.0 document
>
>
>As per the last meeting, here is my suggestion for an addition to the
>introduction of the systemVerilog document.
>
>As discussed, the idea was to give some credit in the document for the
>development and the donation.
>
>replace first sentence with this paragraph:
>
>"This document specifies the Accellera extensions for a higher level of
>abstraction for modeling and verification with the Verilog Hardware
>Description Language. Much of the syntax and semantics in these extensions
>are part of the SUPERLOG Extended Synthesis Subset (ESS) donation made to
>Accellera by Co-Design Automation, Inc and proven with their products.
>SUPERLOG was developed by Peter Flake and Simon Davidmann to extend Verilog
>into the systems space and the verification space and was built on top of
>the work of the IEEE Verilog 2001 committee."
>
>Simon
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