Subject: SystemVerilog 3.0 - Question about constant declarations
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Fri Jun 21 2002 - 13:31:14 PDT
Hi, Gilford -
This looks like an oversight on the part of the SystemVerilog committee. I
would think that multiple constants would be permitted but let me throw
this to the committee email reflector to see somebody has a different opinion.
Thanks for asking the question. Seems like we should either correct this or
clarify in the spec that this is different from most Verilog declaration
styles.
Regards - Cliff Cummings
>From: Gilford, Mick [mailto:mick_gilford@mentorg.com]
>Sent: Wednesday, June 19, 2002 8:19 AM
>To: Brophy, Dennis
>Subject: RE: Approved Accellera SystemVerilog 3.0 Specification
>
>Question 1
>==========
>I notice that the syntax for constant declarations does not allow a list
>of constants to be declared, whereas for variables (or almost any other
>declaration) a list of assignments is allowed; is this intentional?
>Thus:
> integer var1=1, var2=2;
>is valid, but:
> const integer cons1=1, cons2=2;
>is not.
>
>See LRM p104, A.2.1.3 Type declarations:
> constant_declaration ::= const data_type const_assignment
>
>I would have expected:
> constant_declaration ::= const data_type list_of_const_assignments
>
>Is there a reason for this?
>Is this aspect of the language likely to be made more regular in a future
>release of the standard?
>
>Thanks for your help,
>--Mick
----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
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