Subject: RE: Question on timeprecision
From: Tom Fitzpatrick (fitz@co-design.com)
Date: Fri Jul 27 2001 - 11:38:34 PDT
Hi David,
Because Superlog allows times with or without units, it must have a default
timescale.
Like Verilog, however, time is a 64 bit integer based on the
precision. The smallest precision is 1fs.
For Verilog compatibility, rounding effects occur for both unit and
precision.
I hope this answers your question.
-Tom
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> -----Original Message-----
> From: owner-vlog-pp@eda.org [mailto:owner-vlog-pp@eda.org]On Behalf Of
> David Smith
> Sent: Thursday, July 26, 2001 5:13 PM
> To: 'vlog-pp@eda.org'
> Subject: Question on timeprecision
>
>
> Greetings,
>
> I am reviewing the discussion we had in the last meeting and
> rereading the Superlog_ESS document.
>
> I have a question on "timeprecision" that I would like either
> confirmation or clarification on.
>
> On page 11 it states that "The time step is set globally to the
> smallest precision, as in Verilog, or to 1fs if no timeprecision isused.".
> This states the result on the time step if no timeprecision is
> specified (and one assumes that there is no value set using `timescale).
>
> My question is what happens to the rounding? It would appear
> that, since the time step controls the resolution of events it
> would also effect
> the rounding of the value. This is not explicit (perhaps obvious).
>
> Thanks
> David
>
> David W. Smith
> Architect
>
> > Avant! Corporation
> 9205 SW Gemini Drive
> Beaverton, OR 97008
>
> Voice: 503.520.2715
> FAX: 503.643.3361
> Email: david_smith@avanticorp.com
> http://www.avanticorp.com
>
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