Subject: RE: FW: Verif Guild - Vol 3, no 09
From: Erich Marschner (erichm@cadence.com)
Date: Tue Jun 04 2002 - 09:19:13 PDT
Vassilios,
Bernard is indeed a consultant, and he works for various companies. However, it is inappropriate to assume that all comments made by consultants are paid for by someone else. I've worked with Bernard for some time in the context of the Formal Verification Technical Committee, and he has consistently spoken his own mind, without regard to the preferences of those he has contracted with. I respect him for being willing to voice his own opinion, and I would expect and encourage others to do so as well. Let's not stoop to paranoia and innuendo here - let's focus on accomplishing the purpose of this committee.
Regards,
Erich
-------------------------------------------
Erich Marschner, Cadence Design Systems
Senior Architect, Advanced Verification
Phone: +1 410 750 6995 Email: erichm@cadence.com
Vmail: +1 410 872 4369 Email: erichm@comcast.net
| -----Original Message-----
| From: Vassilios.Gerousis@Infineon.Com
| [mailto:Vassilios.Gerousis@Infineon.Com]
| Sent: Tuesday, June 04, 2002 11:31 AM
| To: davek@co-design.com; Shalom.Bresticker@motorola.com
| Cc: vlog-pp@eda.org
| Subject: RE: FW: Verif Guild - Vol 3, no 09
|
|
| Bernard is a consultant. I wonder who is paying/feeding him
| to say these things. Some of the phrases sound familiar.
|
| -----Original Message-----
| From: Dave Kelf [mailto:davek@co-design.com]
| Sent: Tuesday, June 04, 2002 3:10 PM
| To: Shalom Bresticker
| Cc: vlog-pp@eda.org
| Subject: Re: FW: Verif Guild - Vol 3, no 09
|
|
| Hi Shalom
|
| Many thanks. Actually I think Stu has sent a nicely worded
| reply to Jannick
| already
|
| Thanks for looking out for us
|
| Dave
|
|
|
| At 02:01 PM 6/4/2002 +0300, Shalom Bresticker wrote:
| >A criticism of SystemVerilog.
| >(Note: Bernard is active on the VFV committee.)
| >
| >Shalom
| >
| >
| >-----Original Message-----
| >From: Janick Bergeron
| >[<mailto:janick@bergeron.com>mailto:janick@bergeron.com]
| >Sent: 04 June 2002 11:23
| >Subject: Verif Guild - Vol 3, no 09
| >
| >( VG 3.09, Item 8, re: VG 3.08, Item 10 )
| ---------------------- [02/06/04]
| >
| >From: Bernard Deadman [bdeadman@sdvinc.com]
| >
| >I've been reading the proposed SystemVerilog 3.0 (aka Superlog)
| >specification which, if the Accellera reflector is to be
| believed, is
| >being prematurely rushed out to allow an announcement at DAC.
| >
| >It seems bizarre to me that this language apparently addresses the
| >same issue, yet it's not remotely close to Object Oriented. In fact
| >the proposal is still non-ANSI C-like, just as Superlog is, without
| >classes, without dynamic allocation of any kind and most peculiarly
| >without pointers! Even something like manipulating an arbitrary
| >length queue of expected result structures is going to be more
| >difficult, and less efficient than it needs to be.
| >
| >I know you can't synthesize all of ANSI-C let alone C++,
| but many 21st
| >Century testbenches are easier and cheaper to build with these
| >features. Frankly I wonder is the energy going into this process is
| >worthwhile and if we wouldn't all be better off with full
| integration
| >of C++ class libraries into HDL simulators? At least that solution
| >would be vendor independent, require minimal specialised
| learning and
| >have a reasonable lifespan! Unify that solution in NC-Sim,
| ModelTech
| >and VCS and who cares about Superlog?
| >
| >I was very pleased to see the announcement from Cadence this week
| >(<http://www.cadence.com/company/pr/052002_SFV_Verification.
| html>http://www.cadence.com/company/pr/052002_SFV_Verification.html)
| >that
| >"Native support of SystemC in the Cadence?(r) NC-Sim
| simulator will enable
| >designers to mix SystemC, RTL, and analog mixed-signal descriptions.
| >Designers also can view waveforms and hierarchy; control
| their C/C++,
| >Verilog and VHDL code; and easily debug in a powerful
| environment that
| >offers mixed simulation of SystemC, Verilog, Verilog-A,
| VHDL and VHDL-A
| >open languages. Cadence supports TestBuilder verification
| extensions to
| >SystemC 2.0. These enable designers and verification
| engineers to write
| >reusable testbenches quickly and concisely at a high level
| of abstraction
| >in C/C++."
| >
| >I think this is great news and offers a *LOT* more scope for
| >development than Superlog. It's a competitive business so
| my guess is
| >Synopsys and Model Tech. won't be far behind!
|
| ______________________________
|
| Dave Kelf
| VP Marketing
| Co-Design Automation, Inc.
|
| Tel: 1 877 6 CODESIGN ext 404
| Mobile: 1 617 571 9883
| Fax: 1 781 662 2281
| Email: davek@co-design.com
| Web: www.co-design.com
| www.superlog.org
|
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| http://www.co-design.com/news/index.htm
|
| "Faster, Smarter Verilog"
| ______________________________
|
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