Subject: RE: FW: Verif Guild - Vol 3, no 09
From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Tue Jun 04 2002 - 11:57:11 PDT
Vassilios and Erich,
I may be out of line here, and probably should not be sending this to the
entire Verilog++ reflector. But your messages regarding Bernard's post to
the Verification Guild went to the reflector, and so I feel this needs to
be said. I was hoping someone else would pipe up first, and save me any
embarrassment...
Vassilios, this is just my opinion, but I think you've taken offense where
none was intended, and are now conducting a personal witch hunt when there
are no witches to be found. I feel that some of your innuendos are
completely out of line, and should not be posted to the Verilog++
reflector. They most certainly do not express my viewpoint.
I have five children, and occasionally the bickering and grudge holding
between them get to be so much that I wish I could lock the ones that keep
accusing each other into a padded room until they work it out. A sound
proof room, so that I won't have to listen to the "discussion". I am
having those same feelings at this moment. I, for one, am very tired of
hearing this bickering regarding Cadence's support for SystemVerilog!
Erich and his fellow engineers at Cadence have raised some legitimate
concerns regarding how to best implement SystemVerilog, and how to improve
its capabilities. As a member of the SystemVerilog standards group, I want
to see these concerns addressed in a professional and technical manner.
I don't think Erich ever intended to attack the SystemVerilog standard or
slight in any way the individuals that helped define the standard. In
fact, looking back at some of the e-mails the past couple of weeks, I think
Erich and Cadence have acknowledged that SystemVerilog is making a
significant contribution the Verilog and system design community. I never
interpreted Erich's e-mails as anything but legitimate concerns and
questions. The English language, however, is infamous for having the
intent behind the same words interpreted differently by different
readers. Amongst my circle of friends and colleagues, I am just as well
known for thinking I said one thing, and having someone else hear a
completely unintended message. I hope this e-mail is not one those that
gets misinterpreted.
It may be that the way in which Erich raised his initial concerns was
poorly worded or poorly timed, but I do not think any offense or belittling
was intended. Nor do I think there was--or is--any individual or corporate
plot to stall or kill SystemVerilog. Erich's initial suggestion on behalf
of Cadence to delay voting on the SystemVerilog 3.0 standard was based on
not knowing the full time line, and that SystemVerilog 3.0 was establishing
a baseline rather than a final standard. Once that was understood, he and
his fellows at Cadence made it very clear that they support the process and
want to work with the standards group to ensure the final SystemVerilog 3.1
standard is as robust as can be. Erich has also made it clear that
Cadence's abstention on voting on SystemVerilog 3.0 was based on Cadence as
a company having failed to give adequate time and resources to reviewing
the standard. It was NOT a vote against SystemVerilog. Cadence has now
pledged more resources towards SystemVerilog standardization than some of
the other major EDA companies. I see that as a much louder vote of YES for
SystemVerilog than the no-impact abstention.
Vassilios, it is time to put any personal feelings aside and focus on the
positive. Cadence has stated they are interested in SystemVerilog. Please
forgive and forget any offense--whether intentional or not--that you may
have read in past e-mails, and look at the technical message.
Of course, we could see if there is a padded room available at DAC that
could be used to resolve this perceived dispute ;) A sound proof room. I,
for one, do not want to hear any more negative "discussion"!
Stu
At 09:19 AM 6/4/2002, Erich Marschner wrote:
>Vassilios,
>
>Bernard is indeed a consultant, and he works for various
>companies. However, it is inappropriate to assume that all comments made
>by consultants are paid for by someone else. I've worked with Bernard for
>some time in the context of the Formal Verification Technical Committee,
>and he has consistently spoken his own mind, without regard to the
>preferences of those he has contracted with. I respect him for being
>willing to voice his own opinion, and I would expect and encourage others
>to do so as well. Let's not stoop to paranoia and innuendo here - let's
>focus on accomplishing the purpose of this committee.
>
>Regards,
>
>Erich
>
>-------------------------------------------
>Erich Marschner, Cadence Design Systems
>Senior Architect, Advanced Verification
>Phone: +1 410 750 6995 Email: erichm@cadence.com
>Vmail: +1 410 872 4369 Email: erichm@comcast.net
>
>| -----Original Message-----
>| From: Vassilios.Gerousis@Infineon.Com
>| [mailto:Vassilios.Gerousis@Infineon.Com]
>| Sent: Tuesday, June 04, 2002 11:31 AM
>| To: davek@co-design.com; Shalom.Bresticker@motorola.com
>| Cc: vlog-pp@eda.org
>| Subject: RE: FW: Verif Guild - Vol 3, no 09
>|
>|
>| Bernard is a consultant. I wonder who is paying/feeding him
>| to say these things. Some of the phrases sound familiar.
>|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com
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