Subject: Re: Unions - overlaying bits & logic
From: Kevin Cameron (Kevin.Cameron@nsc.com)
Date: Wed Apr 10 2002 - 11:08:55 PDT
> Kevin,
>
> Normal unions do not define the data storage, so writing one member and reading another is not recommended because it is implementation dependent. However we all know that this kind of "dirty" operation is sometimes useful, and the packed union defines a limited version which has a standard behavior.
Er.. I do that kind of thing quite often, and I'm sure the folks that write embedded stuff on small machines do more of it. It may
be dependent on machine endianess but it is well defined. FYI, the last time I used it was writing verification code for a USB
controller a few months ago - the host-controller list processing overlays various record types.
> I sent the following on 17 March. It uses the word "masked" to mean 4 state.
>
> A packed union contains members that are packed structures or arrays of the same size. This ensures that you can read back a union member that was written as another member. If any member is masked, the whole union is masked. A packed union can also be used as a whole with arithmetic and logical operators, and its behavior is determined by the signed or unsigned keyword, the latter being the default.
>
> For example, a union can be accessible with different access widths:
> typedef union packed { // default unsigned
> s_atmcell acell;
> bit [423:0] bit_slice;
> bit [52:0][7:0] byte_slice;
> } u_atmcell;
>
> u_atmcell u1;
> byte b; bit [3:0] nib;
> b = u1.bit_slice[415:408]; // same as b = u1.byte_slice[51];
> nib = u1.bit_slice [423:420]; // same as nib = u1.acell.GFC;
>
> Note that writing one member and reading another is independent of the byte ordering of the machine, unlike a normal union of normal structures, which are C-compatible and have members in ascending address order.
>
> Peter.
That goes back to the packing issue - just saying the union members are the same size doesn't indicate how
the data is stored. Is it always LSB/right-index first (C little endian)? - in which case the LRM should
say so, and it would then not be a problem to have different size objects in the union:
union {
char tag;
struct {char tag; char dataC[15:0]} DC;
struct {char tag; real dataF[1:0]} DF;
} Pkt;
Pkt.tag, Pkt.DC.tag and Pkt.DF.tag are equivalent. The size of the union is that of the largest member.
Data alignment in C is also machine dependent, as addressing usually depends on data size. Since
System Verilog is not constrained by implementation the data should not be padded, i.e. in the
Pkt union above Pkt.DC.dataC[7:0] is the same data as Pkt.DF.dataF[0:0] (C would normally
add 7 bytes of padding before dataF).
If the packing is defined the 'packed' union syntax is redundant, you can always add a member describing
the whole union if you want to do arithmetic on it as a whole (provided it's all masked or all non-masked).
I think we agree that you can't overlay masked and non-masked data, but I don't think we can
outlaw mixing masked and non-masked in structs which may be overlayed. The restriction
should only be that masked can only overlay masked, and non-masked overlay non-masked,
i.e. this is illegal:
union {
struct { char tag; logic [128:0]L; } A;
struct { char tag; real R[2];} B;
}
but this is OK:
union {
struct { char tag; logic [128:0]L; } A;
struct { char tag; logic [63:0]R[2];} B; // use bitstoreal !
}
--Thinking back to the USB controller, it may be desirable to state the packing/alignment explicitly in SystemVerilog for software compatibility, default being no-padding/little-endian) e.g.:
struct align(64) // struct starts on 64 bit boundary // if/when mapped to addressable hardware align(32,shortreal) // 32bit addressing for reals align(8,char,big) { // big-endian byte-aligned chars // 3 bytes padding char tag; shortreal sr; } bus;
That capability would have been handy because the USB controller was for an X86 machine but the (C) testbench was running on Solaris (Sparc - 64bit/big-endian), moving data from the Verilog to the C was a pain.
Something for 3.1?
Kev.
> At 11:21 AM 4/9/02 -0700, Kevin Cameron x3251 wrote: > > >> Wouldn't mind a response from Co-Design on this before the next meeting. >> >> Ta, >> Kev. >> >> > Apart from endianess, there is an issue with size of data in unions. The types bit,char,integer etc. are >> > as in C, but types like "logic" do not have a defined bit representation - it could be: >> > >> > A: an enum (e.g. L0=0,L1=1,LX=2,LZ=3) - requires 2 bits (per node) >> > B: value & strength (0,1,X) * (1,Z) - requires 3 bits >> > C: value, strength and certainty (0,1) * (1,Z) * (1,X) - also 3 bits, but different coding >> > >> > I think it is therfore impossible to sensibly overlay logic and bit types, unions should have >> > either all logic or all bit as the base type of all elements. The alternative is to store the >> > X & Z orthogonally so that only the bit value is overlayed (using representation C), >> > which has performance issues. >> > >> > If a union of "structs" is declared, the the fields being overlayed should match in their >> > base type (rather than the whole struct). >> > >> > [Note: 'logic' and 'reg' should probably be something other than 'integer_type' in the BNF] >> > >> > Kev. > > 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> > * Next message: Vassilios.Gerousis@Infineon.Com: "FW: Assertions spec available for review" > * Previous message: Kevin Cameron x3251: "Re: Unions - overlaying bits & logic" > * In reply to: Kevin Cameron x3251: "Re: Unions - overlaying bits & logic" > * Messages sorted by: [ date ][ thread ][ subject ][ author ] > > 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> > This archive was generated by hypermail 2b28 : Wed Apr 10 2002 - 03:36:18 PDT
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