Subject: SystemVerilog - Accellera -vs- IEEE
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Fri Apr 26 2002 - 17:07:30 PDT
Hi, All -
Could someone explain to me when and how the Accellera SystemVerilog effort
is going to be handed off to the IEEE Verilog Standards Group, chaired by
Mike McNamara?
When we first started, I know we said we wanted to pursue the Accellera
path to get a working Standard in place by DAC 2002 and then we would
pursue the IEEE Standardization effort.
I'm not sure what the relative roles are regarding the Accellera effort
versus the IEEE effort. I thought most of the group intended to move with
the Accellera document over to the IEEE standardization effort. I'm not
sure I want to do both since the IEEE document will likely make additional
changes to the Verilog language.
Is there an intent to complete the 3.1 effort by a certain date and disband
in favor of IEEE picking up the ball?
Is there an intention of doing a version 3.2? 3.3? etc.?
Are dueling committees planned?
Does it make sense to role the Accellera effort into an IEEE committee and
let that committee produce checkpoint Accellera draft documents?
Regards - Cliff
----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, Synthesis and Verification Training
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