Subject: Re: FSM Enhancement Goals and Thoughts
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Thu Dec 13 2001 - 14:42:12 PST
At 12:58 PM 12/13/01 -0800, you wrote:
>Cliff,
>
>This example shows the usefulness of (1) hierarchical FSMs, (2)
>supporting external state transfers, (3) fsm spawning, and (4)
>co-operating state machines having different clocks.
>
> >From your e-mail, I understood that we share the feeling that we do
>need some examples to show the various techniques that can be used.
>Indeed, this is an academic example, in that every body understands the
>goal of the design. Of course, if anyone can come with other examples
>so much the better.
Acknowledged.
>Regards,
>Alec
Am I the only one who does not want to see this type of example added to
the SystemVerilog LRM?
The problem I find with most contrived academic examples is that they
rarely lend credibility to the need for a proposed enhancement. The
question becomes, "Do we really need the new syntax or are we just trying
to invent a problem to justify a proposed enhancement?"
If we cannot come up with a real problem that would benefit from a language
enhancement, perhaps the problem is not very prevalent and perhaps the
enhancement is not needed.
I happen to believe Simon and Peter when they say that they have customers
that have benefited from this syntax, and I also know that the same
customers would be very reluctant to share their design issues related to
proprietary designs. This is why I would hope that we could find a industry
standard problem that would be worthy of our efforts.
I can't think of any real designs that handshake control signals between
FSMs that operate in different clock domains. Such a design would be wisely
partitioned into at least two modules, only permitting one clock per module
and add synchronizers (or synchronizer modules) to remove metastability
from the control signals being passed between clock domains (my San Jose
SNUG2001 paper covers this topic with some detail).
I would like to invest my valuable time on a problem that could prove the
value of the new syntax and that we are willing to add to the SystemVerilog
LRM.
What are the wishes of the committee?
Regards - Cliff
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