Subject: Re: FSM Enhancement Goals and Thoughts
From: Adam Krolnik (krolnik@lsil.com)
Date: Thu Dec 13 2001 - 15:11:35 PST
Good afternoon Alec, Cliff;
I agree with Cliff that the example would make it difficult for
designers to relate to what they do. I also think that these
points are interesting and worth persuing, but not all of them
at once:
(1) hierarchical FSMs,
(2) supporting external state transfers
(3) fsm spawning,
(4) co-operating state machines
My thoughts on a fsm example were along the lines of a somewhat
old standby, a Dram controller (or sdram to not appear dated.)
This would be a straightforward FSM that could be coded with
(I hope) sufficient size to be both a good example and yet
not be too difficult.
The other example I thought about in the context of co-operating
fsm's and fsm spawning (pipelined operations) would be a
pipelined (multiple outstanding transaction) bus.
A bus that could have up to 3 outstanding load or store requests,
with a variable data return latency and a store data phase separate
from the address phase. Hmmm, this sounds a little like a PowerPC
interface...
With this kind of example, you could show both a representation
that is similar to current verilog implementations of FSM's,
and a higher level definition that would utiliize fsm spawning,
co-operating FSMs, etc.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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