Subject: Re: FSM Enhancement Goals and Thoughts
From: Alec Stanculescu (alec@fintronic.com)
Date: Thu Dec 13 2001 - 15:51:03 PST
> Am I the only one who does not want to see this type of example added to
> the SystemVerilog LRM?
>
> The problem I find with most contrived academic examples is that they
> rarely lend credibility to the need for a proposed enhancement. The
> question becomes, "Do we really need the new syntax or are we just trying
> to invent a problem to justify a proposed enhancement?"
>
> If we cannot come up with a real problem that would benefit from a language
> enhancement, perhaps the problem is not very prevalent and perhaps the
> enhancement is not needed.
>
We cannot come up with a real problem because real problems are too
complicated and once you solve them well you do not want to give them
for free. However, you can come up with a simple problem, understood
by every one, and which displays the needs of the real
problem. Indeed, thre is the risk that the academic problem is off the
wall and does not display any real needs.
> I happen to believe Simon and Peter when they say that they have customers
> that have benefited from this syntax, and I also know that the same
> customers would be very reluctant to share their design issues related to
> proprietary designs. This is why I would hope that we could find a industry
> standard problem that would be worthy of our efforts.
>
> I can't think of any real designs that handshake control signals between
> FSMs that operate in different clock domains. Such a design would be wisely
> partitioned into at least two modules, only permitting one clock per module
> and add synchronizers (or synchronizer modules) to remove metastability
> from the control signals being passed between clock domains (my San Jose
> SNUG2001 paper covers this topic with some detail).
You are right. However, at a higher level of abstraction, it may be
the case that you do not want to be bothered with the low level
protocol of the synchronizers (Synchronizers, which presumably do not
depend on the particular problem to be solved and are therefore well
debugged), in the same way that you do not want to look at the 30-60
transistors of a flip-flop.
> I would like to invest my valuable time on a problem that could prove the
> value of the new syntax and that we are willing to add to the SystemVerilog
> LRM.
>
That is very true.
> What are the wishes of the committee?
>
> Regards - Cliff
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>
Alec
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