Re: Thoughts about arrays in SystemVerilog

Subject: Re: Thoughts about arrays in SystemVerilog
From: Peter Flake (flake@co-design.com)
Date: Mon Apr 01 2002 - 07:46:27 PST

Kevin,

I agree that packed implies contiguous.

I sent in a previous email:

A packed union contains members that are packed structures or arrays of the same size. This ensures that you can read back a union member that was written as another member. If any member is masked, the whole union is masked. A packed union can also be used as a whole with arithmetic and logical operators, and its behavior is determined by the signed or unsigned keyword, the latter being the default.

For example, a union can be accessible with different access widths:
typedef union packed { // default unsigned
s_atmcell acell;
bit [423:0] bit_slice;
bit [52:0][7:0] byte_slice;
} u_atmcell;

u_atmcell u1;
byte b; bit [3:0] nib;
b = u1.bit_slice[415:408]; // same as b = u1.byte_slice[51];
nib = u1.bit_slice [423:420]; // same as nib = u1.acell.GFC;

Note that writing one member and reading another is independent of the byte ordering of the machine, unlike a normal union of normal structures, which are C-compatible and have members in ascending address order.

Does this meet your requirements?

Peter.

At 02:48 PM 3/26/02 -0800, Kevin Cameron x3251 wrote:

We had some discussion about overlays and endianness, since Verilog is not
compiled to a specific architecture, and pointers are not implemented (yet),
I think we should take "little-endian" as the norm for packing. I.e. running
your Verilog simulation on Sparc vs. X86 should get the same results without
ugly `ifdefs in the source. E.g.:

  union { int         i;
          char        c[3:0];
          bit  [31:0] b;}   reg32;

c[3] always contains the sign bit of 'i' which is also b[31].

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