Subject: RE: BNF question
From: Tom Fitzpatrick (fitz@co-design.com)
Date: Wed Apr 17 2002 - 12:54:50 PDT
Thanks Mac!
-t
> -----Original Message-----
> From: owner-vlog-pp@server.eda.org
> [mailto:owner-vlog-pp@server.eda.org]On Behalf Of Michael McNamara
> Sent: Wednesday, April 17, 2002 3:29 PM
> To: fitz@co-design.com
> Cc: 'Vlog-Pp@Eda. Org'
> Subject: RE: BNF question
>
>
>
>
> Tom Fitzpatrick writes:
> > Hi Gang,
> >
> > Is this legal?
> >
> > module top;
> > integer foo;
> > bit a;
> >
> > task mytask(input logic[99:0] mya);
> > ...
> > endtask
> >
> > initial
> > mytask( {foo{a}} ); // multiple concat with non-constant replication
> > endmodule
>
> Recoding this in Verilog 1364-2001 as:
>
> module top;
> integer foo;
> reg a;
>
> task mytask;
> input [99:0] mya;
> begin
> end
> endtask
>
> initial mytask( {foo{a}} ); // multiple concat with
> non-constant replication
>
> endmodule
>
> Verilog-XL says:
> Compiling source file "ss.v"
>
> Warning! Repetition multiplier in concatenation is not a
> constant expression [Verilog-IRMC]
> "ss.v", 11: {foo{a}}
>
> Warning! Repetition multiplier in concatenation is not a
> constant expression [Verilog-IRMC]
> "ss.v", 11: {foo{a}}
> Highest level modules:
> top
>
> 2 warnings
> 0 simulation events (use +profile or +listcounts option to count)
> CPU time: 0.0 secs to compile + 0.0 secs to link + 0.0 secs in simulation
> End of VERILOG-XL 3.10.s010 Apr 17, 2002 12:05:26
>
> NC Verilog says:
>
> ncprep: v2.2.(s10):
> initial mytask( {foo{a}} ); // multiple concat with non-constant
> replication
> |
> ncvlog: *E,NOTPAR (ss.v,11|19): only parameters and constant
> literals allowed in constant expressions [4(IEEE)].
>
>
> VCS 6.1 says:
>
> Error-[UIMCM] Unknown in multiconcat multiplier
> Multiplier in multiconcats should be a known constant value
> "ss.v", 11: {foo {a}}
> 1 error
>
> ModelTech says:
>
> Model Technology ModelSim SE/EE vlog 5.4a Compiler 2000.04 Apr 18 2000
> -- Compiling module top
> ERROR: ss.v(11): Repetition multiplier must be constant
>
> So, while Verilog-XL only warns, every other tool that I've tried says
> that this is illegal
>
>
> > According to both the 1364-2001 bnf and Stefen's new bnf, the
> > argument to a task can be an "expression", which includes a
> > "primary." The "primary" includes a "multiple_concatenation," but
> > that only allows for a "constant_expression" as the replication
> > specifier.
> >
> > The "{foo{a}}" expression in my example falls under the definition
> > of "variable_concatenation" in both BNFs. The only place I can find
> > this used is as a subterm of "variable_lvalue_item" which is
> > restricted to being on the LHS of an assignment, the target of a
> > force(/etc.), or an increment/decrement expression. Therefore, I
> > conclude that my above example should be illegal.
> >
> > Unfortunately, a customer has run this on XL and NC, and they both
> > allow it. Can someone with access to these simulators verify this
> > (and maybe check VCS too)? Should it be an error? If not, then I
> > fear that Stefen has more work to do 8-).
>
>
> Remember that the BNF is only part of the standard, and it must be
> read in conjuction with the rest of the standard (we could save a lot
> of time and paper were this not the case).
>
> The last sentence of Section 4.1.14 of 1364-1995 states that the
> repitition multiplier must be a constant expression.
>
> In 1364-2001, this sentence was moved up to the beginning of the
> description of the repeat concatenate, and expanded to require that
> the constant expression may not include 'x' or 'z' values.
>
> As for Verilog-XL accepting it, at least the current version (3.10)
> warns that it is illegal.
>
> -mac
>
>
> > Thanks,
> > -Tom
> > ------------------------------------------------------
> > Tom Fitzpatrick
> > Director of Technical Marketing
> > Co-Design Automation, Inc.
> > ------------------------------------------------------
> > Email: fitz@co-design.com Mobile: (978)337-7641
> > Tel: (978)448-8797 Fax: (561)594-3946
> > Web: www.co-design.com
> > www.superlog.org
> > ------------------------------------------------------
> > SUPERLOG = Faster, Smarter Verilog
> > ------------------------------------------------------
> >
>
This archive was generated by hypermail 2b28 : Wed Apr 17 2002 - 12:55:49 PDT