Quotation marks in the SystemVerilog Standard.

Subject: Quotation marks in the SystemVerilog Standard.
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Mon May 06 2002 - 09:51:24 PDT

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Smart quotes in the code examples should be replaced with straight quotes.
This is recommended to avoid questions like "how do I enter the back-ward
double quote into my source file."

It also helps to distinguish single quotes (') from back-tics (`)

Draft 8
Syntax 2-1 - replace smart quotes with straight quotes
Syntax 3-5 - replace smart quotes with straight quotes
Section 17 - (global) replace smart quotes with straight quotes
Annex A - (global) replace smart quotes with straight quotes

Regards - Cliff

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Cliff Cummings - Sunburst Design, Inc.
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