Subject: Editorial Notes SysteVerilog 3.0/draft 9
From: Heath Chambers (heath@trailnet.com)
Date: Tue May 28 2002 - 08:02:46 PDT
Here are some things I found in reviewing draft 8 and draft 9. The first one is
real minor, but the second two could lead to confusion.
SystemVerilog 3.0/draft 9
Section 13.6
Example
Indent a.slaveWrite; inside of module memMod
under the else (second to last line of module).
SystemVerilog 3.0/draft 9
Section 14.1
Paragraph 2 Bullet 2
For parameter redefinition, change:
foo #(name=value, name=value) u1(...); TO
foo #(.name(value), .name(value)) u1(...);
SystemVerilog 3.0/draft 9
Section 18.2
Paragraph 5
For parameter redefinition, change:
(parameter_name=value) TO
#(.parameter_name(value))
Thanks,
-- Heath
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