Subject: RE: An Update
From: Erich Marschner (erichm@cadence.com)
Date: Tue May 28 2002 - 05:22:22 PDT
Vassilios,
Erich could you please send me the list we accumulated during our last meeting.
I assume you mean the list of issues. The latest draft is still being reviewed here at Cadence, and there may be additional issues that come up as a result. I'll forward the list to the reflector, as we agreed in the meeting, as soon as it is complete. I suspect that will be around the end of this week.
Regards,
Erich
-------------------------------------------
Erich Marschner, Cadence Design Systems
Senior Architect, Advanced Verification
Phone: +1 410 750 6995 Email: erichm@cadence.com
Vmail: +1 410 872 4369 Email: erichm@comcast.net
| -----Original Message-----
| From: Vassilios.Gerousis@Infineon.Com
| [mailto:Vassilios.Gerousis@Infineon.Com]
| Sent: Saturday, May 25, 2002 11:45 AM
| To: vlog-pp@eda.org; assertion@eda.org
| Cc: lynnh1@ix.netcom.com; georgia@valleypr.com
| Subject: An Update
|
|
| Hello Everyone,
| Last week, Stu got a few correction typos, etc. This
| means that the draft is becoming stable and ready for
| publication and use. Our deadline for final edit (Typos) is
| May 29. Any input beyond that will be delayed until 3.1
| activities. We do plan to generate a clean document, and
| call that SystemVerilog 3.0 Standard. It will be sent to
| Lynn for paper copies to early participants and Board members.
| I am still working on logistics for our meeting on June
| 5th. I will try to get an early agenda early next week.
| Please welcome Stuart Swan of Cadence, latest member to
| the Verilog++ committee.
| Erich could you please send me the list we accumulated
| during our last meeting.
|
| Planned Activities At DAC.
| a- We intend to have a gathering at 3:00 PM at DAC to
| present latest details on SystemVerilog by our great
| contributor Stuart Sutherland. If you know of anyone who
| will be at DAC and wants to know about SystemVerilog, please
| send him/her to the Accellera member room.
| b- We also plan hold bird of a feather session, I think
| at 5:30 to 6:30 PM just before the DAC party. Dave Kelf
| will help prepare logistics. Stuart we will need you again
| to present.
| c- Dave Kelf is also planning to present at the
| membership meeting at 10:00 at Accellera room at DAC. I
| would like to ask companies or representative who plan to
| implement SystemVerilog 3.0 to send me a private message and
| I will add you on the list to be presented at DAC.
|
| Our deepest thanks and appreciation (Dave Kelf, Tom
| Fitz, David Lacey and I) for the Verilog++ and the Assertion
| teams (i.e. SystemVerilog 3.0 team). This has been a very
| cooperative, focused, and hard working SystemVerilog team.
|
| Best Regards
|
| Vassilios
| -------------------------------------------------------------
| -----------------------------------------------------------------
| Dr. Vassilios Gerousis Infineon Technologies
| DAT
| CAD, MchB
| Telephone: +49-89-234-21342 BalanSt. 73
| Fax: +49-89-234-23650 D-81541 Munich
| email: Vassilios.Gerousis@infineon.com Germany
| Site Map:
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str%2E;HNR=73
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