Subject: Voting Results as of 5/30 by the Accellera Board
From: Vassilios.Gerousis@Infineon.Com
Date: Thu May 30 2002 - 08:38:54 PDT
Dear HDL+ members,
As of early morning today the quorum of the Accellera board (7 members) have voted. We still have few members who did not vote yet, and the voting will close by June 3rd. We want to give remaining members until Monday, to cast the vote.
SystemVerilog 3.0 can be considered approved by the Accellera Board. This is not official until we obtain the full votes. So please keep it within the committee. As of today, we have the following votes:
Antrim - approve
Avant! - approve
Cadence - abstain
Co-Design - approve
Forte - has not voted.
Mentor -approve
Motorola - have not voted yet.
NEC - approve
Sun - has not voted.
Synopsys - approve.
Verisity - approve
Congratulation! SystemVerilog 3.0 is can be consider an Accellera approved standard by the bylaws.
This a record accomplishment by a standardization body to build a standard on a proven technology within one year. Despite the continuos critique of one company, I am
proud of this team the hard work, and the excellent results that you have shown in the last year.
1- This team has shown a great effort by working together in an excellent spirit and enthusiasm that I have not seen in other working groups.
2- Each one of you had put extra hours, your own time and in few cases, your personal money in developing and enhancing the different features of what SystemVerilog now stands for.
3- Each one of you have their specific expertise, and helped each other to strengthen this expertise. You have shown good reasons in your arguments as well as good reasons to adjust and modify what we have today.
4- The committee has shown good cooperation with no negative until we experienced it from the outside of this committee.
5- Every milestone we set and agreed upon, we accomplished on time.
6- Although the core of SystemVerilog comes from Co-Design, Verplex and Real Intent, every portion bears the marks of every person in this committee.
7- I have valued the no-nonsense enthusiasm of the IEEE Verilog members and the extremely valuable contribution you have provided.
8- Unlike many committees, our committee is extremely balanced with users experience (Cliff, Stu, Stephen, Enders, Adam, Kevin, etc.). Many of you have voiced and introduced the needs of other users like Intel, HP, CISCO, etc within SystemVerilog. The star operator is an example, as well as what Cliff has done in finite state machine modeling. The claim by a company that this is not a user driven is a shame.
8- Above all, you have endured my leadership in a good spirit.
Despite what few individuals continue to say, SystemVerilog 3.0 is an excellent technical document. The committee with the blessing of the majority of the board have built and delivered the proper scope of SystemVerilog. The committee have made the conscious effort to stop, and voted to postpone issues until 3.1. This is the collective and the majority judgement of SystemVerilog (Verilog++ and assertion). The decision is done and complaining should stop.
I hope that the same cooperation and the wonderful spirit will continue through the making of SystemVerilog 3.1. As we go into the planning process, I will rely more heavily on people who are implementing 3.0 than just providing opinions. We will have several focus areas which are:
1- Committee approved issue list.
2- Feedback from companies implementing 3.0.
3- Additional enhancements that members would like to see.
Please help me to make this committee and its deliverable as good as the current committee. I will help everyone who wants to work with us to improve Verilog. However, I will not tolerate delaying tactics and continuous negative propagandize.
Best Regards
Vassilios
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Dr. Vassilios Gerousis Infineon Technologies
DAT CAD, MchB
Telephone: +49-89-234-21342 BalanSt. 73
Fax: +49-89-234-23650 D-81541 Munich
email: Vassilios.Gerousis@infineon.com Germany
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