Subject: June 5 HDL+ Committee Meeting At Synopsys Building B Mountain Vie w
From: Vassilios.Gerousis@Infineon.Com
Date: Thu May 30 2002 - 22:58:06 PDT
> Hello Dear Verilog++ and Assertions committees members,
> Synopsys has agreed to host our meeting and also to host our teleconference for June 5th, 2002. Here are details
>
> 1- Place: Synopsys (Mountain View) - Building B in the Amethyst conference room.
> 2- Time: 9:00 AM - 4 PM.
> 3- Date: June 5, 2002.
> 4- Teleconference Information are:
> International participants: 734-414-0268
> Domestic participants: 877-300-8186
> Participant code: 810623
>
> Agenda:
>
> 1- Introduction --- 9:00 - 9:30 AM.
> 2- List of the Accellera SystemVerilog Committee Issues (Assertion+Verilog+) that the committee has put together for the last year.
> 3- List Of Issues Generated By Accellera Board Members:
> a- Cadence.
> 4- Assertions (OVL) Plans -- 10:00 - 10:30. -- David Lacey
> 5- SystemVerilog 3.1 Plans -- 10:30 - 11:00.
> 6- Proposed enhancements and related proposals: two hours.
> a) Testbench features
> b) Unified Assertions will start at 2:00 pm
> c) C interface
> d) Extended API
7- Planning, milestone development, scheduling 3.1, etc. 3:00 PM - 4:00 PM
> Time may change based on breaks, lunches, etc.
>
> Best Regards
>
> Vassilios
>
> ------------------------------------------------------------------------------------------------------------------------------
> Dr. Vassilios Gerousis Infineon Technologies
> DAT CAD, MchB
> Telephone: +49-89-234-21342 BalanSt. 73
> Fax: +49-89-234-23650 D-81541 Munich
> email: Vassilios.Gerousis@infineon.com Germany
> Site Map: http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2E;HNR=73
> ----------------------------------------------------------------------------------------------------------------------------------
>
>
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