Re: Jeda Language


Subject: Re: Jeda Language
From: Simon Davidmann (simond@co-design.com)
Date: Tue Nov 20 2001 - 05:22:50 PST


My quick assessment

1) this is competitive language to Vera - competes with the way Vera was
about 3 years ago (ie no temporal logic etc)
2) it currently is a PLI addon capability - and is not the direction that
we have been going in - adding to Verilog
3) it is true openSource - unlike Vera (openDoc)
         being openSource - I am not sure how Accellera can make use of
true openSource stuff - we should ask Karen Bartleson to investigate?
4) It is a dynamic verification language - somewhat derived from C/C++
5) from what I can see there are no commercial vendors utilizing it
6) it is not synthesizable
7) it is not based on Verilog

so - my take

The current work in the HDL+ committee is in the synthesizable area and the
draft 2.0 has been accepted
The next phase of work for us all is in the Assertions area - starting Jan2002
what this HDL+ committee starts on in July 2002 is still not defined - and
so we should consider looking into this then.

There are some interesting things in Jeda and my take is that they are not
relevant to what we are doing in the HDL+ committee at the current time.

Vassilios - if you want to get them involved now - my suggestion is to get
them involved with Brian's C language working group - to extend it to
include some Verification features from Jeda.

What are other peoples views?

Simon.

At 02:50 AM 11/20/2001, Vassilios.Gerousis@Infineon.Com wrote:
>Hello V++ committee members,
> I was contacted to examine the JEDA language which seems to offer
> many
>things that System Verilog is planning to offer. I would like the team to
>examine this
>and see what things that we see valuable to use from this "true open source".
>
>http://www.jeda.org/
>
>I will contact the author and see if he wants to participate in our
>activities. I would
>also appreciate any analysis on the language:
>
>1- Can we borrow some of the OO capabilities that JEDA is demonstrating?
>
>2- Do we see some additional verification constructs that we need to borrow?
>
>3- What about the dynamic features of Jeda?
>
>4- Will the PLI provide by JEDA help in System Verilog ?
>
>5- etc.
>
>Best Regards
>
>Vassilios
>
>------------------------------------------------------------------------------------------------------------------------------
>Dr. Vassilios Gerousis Infineon Technologies
> DAT CAD, MchB
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