Subject: RE: Assertions spec available for review
From: Harry Foster (harry@verplex.com)
Date: Fri Apr 26 2002 - 23:46:24 PDT
>
> Please pardon my ignorance for asking basic question.
>
> Regardless of which assertion language is selected by Accellera,
> ( I don't have love or hate any assertion language )
> Is it expected that user will write two sets of assertions,
> or interpretations of specification :
> 1) In System Verilog for Dynamic simulation
> 2) in "SUGAR" For formal checking
>
No--it depends on the stakeholder. First off, keep in mind that Sugar is a
declarative language, while the SystemVerilog DAS are procedural assertions.
The SystemVerilog DAS procedural language (along with the OVL), is really
all the design engineer needs when defining assertion during implementation
at the RT-Level. However, I maintain (from a system perspective) that a
declarative language like Sugar is still needed by both the verification
engineer and the system architect. For example, from a system architect's
point of view, a "functional constraint driven design methodology" is
attractive. In other words, the architect defines (and refines) a
high-level architectural model into block-level components whose interfaces
are specified (or partially specified) in a declarative fashion--using
Sugar. These interface specs serve as monitors during the RTL integration
for system simulation. They could serve as specs for a cycle-based
constraint driven simulation environment at the block-level. Finally, they
could serve as block-level constraints in formal. Note that OVL and DAS are
insufficient and not expressive enough to specify block-level interface
constraints. However, they are still critical elements of an assertion-based
verification strategy (by addressing white box coverage when embedded
directly in the designer's RTL).
Both the SystemVerilog assertion and the SUGAR declaritive formulas can be
used in either dynamic or static verification. It depends on the
stackholder (e.g., designer, verification engineer, or architect).
> Now that Accellera have chosen one language for assertions,
> does this group plan to look and use its syntax to be part of
> SystemVerilog? Can the same set of assertions be used for
> dynamic simulations ?
>
> Ideally one would expect to write the one set of assertions
> used for dynamic and formal verification.
> At minimum don't we want to provide similar or consistent
> syntax , look and feel ?
Work has already begun in coordinating the SystemVerilog and Sugar syntax.
The good thing is that they really aren't that far off...
-Harry
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