Subject: Re: Assertions spec available for review
From: Jayant Nagda (jayantn@cupertino.synopsys.com)
Date: Fri Apr 26 2002 - 18:27:45 PDT
Please pardon my ignorance for asking basic question.
Regardless of which assertion language is selected by Accellera,
( I don't have love or hate any assertion language )
Is it expected that user will write two sets of assertions,
or interpretations of specification :
1) In System Verilog for Dynamic simulation
2) in "SUGAR" For formal checking
Now that Accellera have chosen one language for assertions,
does this group plan to look and use its syntax to be part of
SystemVerilog? Can the same set of assertions be used for
dynamic simulations ?
Ideally one would expect to write the one set of assertions
used for dynamic and formal verification.
At minimum don't we want to provide similar or consistent
syntax , look and feel ?
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