Subject: December 7, Verilog++ Committee Meeting - Reminder
From: Vassilios.Gerousis@Infineon.Com
Date: Thu Jan 03 2002 - 21:57:03 PST
Hi Verilog++ Committee,
Happy new year and for some of us, we still have to celebrate Christmas (Greek
calendar). Our next meeting is planned for December 7. Here are some
Phone number and time: 1 405 244 5555 access code 3715. Meeting time is 9:00am PST,
12:00pm EDT, 5:00pm GMT, 6:00pm EuroCentral.
Thanks for Co-Design for Sponsoring Our Conference Calls !!
Agenda:
1- Review Last meeting minute.
2- Review Action Items.
3- Technical Agenda: We will focus on Issues that has been raised so far in the last year.
a- Rules for always_comb (Boyd Email)
b- Mismatch on connection what should happen.
b- $ root.
c- State Machines (Cliff)
d- Interface Section (Cliff)
e- BNF discussion: All.
f- Others? Please let me know
4- Next Meeting and Agenda.
Best Regards
Vassilios
------------------------------------------------------------------------------------------------------------------------------
Dr. Vassilios Gerousis Infineon Technologies
DAT CAD, MchB
Telephone: +49-89-234-21342 BalanSt. 73
Fax: +49-89-234-23650 D-81541 Munich
email: Vassilios.Gerousis@infineon.com Germany
Site Map: http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2E;HNR=73
----------------------------------------------------------------------------------------------------------------------------------
This archive was generated by hypermail 2b28 : Thu Jan 03 2002 - 22:04:53 PST