Subject: Proposal: Deprecate procedural assign-deassign
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Mon Oct 22 2001 - 08:42:20 PDT
Deprecate procedural assign-deassign
I don't know the formal wording but I propose that we vote to deprecate
procedural assign-deassign statements. Some of the most gosh-awful models
have been written with these infinitely abusable statements that at first
glance appear to be similar to a continuous assignment statement.
I think every new Verilog user at some time has placed an assign statement
inside of an always block where no assign statement was required and either
got lucky on the behavior or confused.
The concept of taking control of a variable with a procedural assign
statement that updates the LHS anytime the RHS variable changes, even if
the RHS variable is not in the sensitivity list is pretty strange. The
concept that last assign wins is also confusing and restoring other
non-assign procedural assignments to activity after a deassign statement is
similarly confusing. I have worked with customers that had to translate
their old assign-deassign Cadence Synergy code into synthesizable code for
Synopsys and Synplicity with multiple assign statements spread throughout a
large model. Ultimately, I could not figure out what the assign priorities
were within the code.
The force-release commands do the same thing but they are rarely abused,
not synthesizable by any tool, and rather clearly documented to be mostly
for debugging purposes.
Having both assign-deassign and force-release where the latter has higher
priority and can also assign to wire types has always been confusing to new
users.
I would like to see this committee take a stand for sanity and deprecate
procedural assign-deassign.
Regards - Cliff
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