Subject: Assignment statement versus assignment operator
From: David Smith (david_smith@avanticorp.com)
Date: Wed Aug 01 2001 - 08:57:41 PDT
I would like to follow up on a discussion we had at the last meeting. The question was raised about the behavior of the assignment group of operators, how they were used, and the meaning of being right or left associative.
The example on page 21 of SUPERLOG_ESS_3.doc is:
if ((a-b)) b = (a+=1)
The previous statement is:
"Note that such an assignment must be enclosed in parenthesis to avoid common mistakes such as a=b for a==b or a|=b for a!=b."
From this we concluded that:
a = b = a+=1
is not a legal Verilog. The analysis is based on the difference between the "assignment statement" (which is NOT an operator and therefore does not have associativity rules) and the "assignment operator" (which is right associative within the new specification).
The need for the parenthesis, as stated above, is not based on the ability to parse the language but on the desire to disambiguate the assignment operator and the the logical comparison operators. This is clearly true for the use within the condition of an selection or iteration statement. It is less clear of the reason for the use of the parenthesis for the assignment statement. I believe we need to make a clearer statement for this case.
The question of whether the following is legal was not discussed.
a = (b = c = a+=1)
Based on the description in the document, the specification that the assignment operator is right associative, and the discussion on page 21 I would conclude that it is. This is due to the ambiguity in the quote above. So, is this a legal use or is the quote above meant to indicate that whenever the result of an assignment operator is used it must be placed within parenthesis? If so, why?
David
David W. Smith
Architect
> Avant! Corporation
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