Subject: Re: bump operators. How do we size the '1'
From: Stefen Boyd (stefen@boyd.com)
Date: Wed Aug 01 2001 - 10:32:42 PDT
At 07:16 PM 7/31/2001 -0700, Stuart Sutherland wrote:
>The point is how many bits wide is the a++ or ++a operation in Verilog,
>not in C.
I think self-determined is what we need. But if it's
self-determined:
module top;
bit [3:0] a, b;
bit [4:0] c;
initial begin
a = 4'hF;
b = 2;
c = ++a + b;
$display("a=0x%h, b=0x%h, c=0x%h",a, b, c);
a = 4'hF;
b = 2;
c = a++ + b;
$display("a=0x%h, b=0x%h, c=0x%h",a, b, c);
end
endmodule: top
will display something like:
a=0x0, b=0x2, c=0x02
a=0x0, b=0x2, c=0x02
Note that ++a will be performed on the 4-bit
value of a and overflow will be discarded before
it is added to b. It only makes sense to try
something other than self-determined if we want
the prefix (postfix won't affect our current
evaluation) operation to be performed at the
size of the rest of the expression.
At 06:14 PM 7/31/2001 -0700, Mac wrote:
>That is because 'answer = (a++)' means assign 'a' to 'answer' and THEN
>increment a after the assignment in complete.
This is what I would expect. It may be new to
the straight Verilog folks, but if we're going
to borrow the ++a and a++ from C, we'd better
follow the same rules.
Regards,
Stefen
--------------------
Stefen Boyd Boyd Technology, Inc.
stefen@BoydTechInc.com (408)739-BOYD
www.BoydTechInc.com (408)739-1402 (fax)
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