Subject: Verilog++ 13th Committee Meeting - 11/26/01
From: Dave Kelf (davek@co-design.com)
Date: Mon Nov 26 2001 - 10:46:21 PST
Verilog++ 13th Committee Meeting
November 26th, 2001
Vassilios leading. DaveK taking minutes
Attendees
(aa-aaaaaaaaaa) Vassilios Gerousis *
(a-aaarar-aaaa) Dave Kelf *
(---aaa--aaaa) John Sanguinetti
(aaaa--a-aa---) Dennis Brophy *
(aaaaaaaaaaaaa) Stu Sutherland *
(-------aaaaa) David Knapp
(aaaaraaar-aaa) Tom Fitzpatrick *
(rraa-aaaaaaa-) Phil Moorby (rep Peter Flake) *
(aaaa-aaaaaaaa) Anders Nordstrom *
(aa--a-aaaaaa) Cliff Cummings *
(aaraaa-aaaaaa) Simon Davidmann *
(aa-aaaaa-a-aaa) Stefen Boyd *
(aaaaaaaaaaaaa) David Smith *
(aaa--a-a--aa-) Mike McNamara *
(aaaaaa) Kevin Cameron *
(a-aa-a) Andy Tsay *
(a) Alex Stantulescu *
First Agenda Item - Review of Draft 3 SystemVerilog Documentation
Page 18 - Attribute syntax still required from PeterF. Peter is targeting
this week to complete this.
Action: Peter to complete Attribute Syntax.
Page 30 - make sure SystemVerilog is fully substituted for Verilog-ACE.
Page 34 - Uncomfortable with putting in non-simulation information - should
be attributes. Example is the state encoding on this page. David S, Cliff
and others disagree. Alternative proposal is to have pre-defined
attributes. Cliff taking action to code up some examples. Peter still to
look at this item given everyone's comments. Everyone need to give this
some more thought for the next meeting.
Action: Cliff to come up with examples as discussed.
Alex Page 37 - minor modification required with example to be moved.
Page 40 - Issues related to scheduling semantics discussion. Compatibility
issues with Verilog2K1. Also issues getting this through IEEE 1364 committee.
Action: Peter Consider this further given the need to make this straight
forward for the IEEE1364 committee.
Page 42 Simon - Fork strobe is an error from legacy SUPERLOG, and needs to
be removed. Stu has details.
Page 43 Peter F - Explanation still required.
Page 47 Simon - $root issue, as previously discussed. Stefen still has
issues with the code complexity that results from $root. Simon / Peter F
plus others think it is OK. Stefen willing to bow to majority to close
issue. Remove red comment from documentation. Agreement that there are
reasons to have $root but it should be constrained. General agreement to
have separate meeting to deal with it specifically.
Page 47/48 $root example require to show abstract model
Action: Simon to write an example.
Page 50 Extern module declaration needed?
Action: Kevin to provide proposal to group
Page 54 Peter needs to provide name space clarification.
Action: Peter to send email to Stu on this.
Page 57 Co-Design needs to add wires to example.
Action: Peter to provide.
Deprecation list to be provided by Cliff for future discussion.
Cliff on BNF - remove <> brackets - inconsistent with previous Verilog
BNFs. Stu to resend BNF again with mentioned changes prior to next meeting.
Title page - remove gap between System and Verilog in SystemVerilog
Documentation should acknowledge SUPERLOG donation - single paragraph near
front.
Next meeting Monday 10th December, usual time and call in number.
Agenda to review document again.
Please provide review comments by email.
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