Subject: Re: State machine encoding (etc.)
From: Kevin Cameron (dkc@galaxy.nsc.com)
Date: Fri Nov 30 2001 - 11:15:11 PST
Since Verilog is a Hardware Description Language as much
as it is a Hardware Design Language, I think it makes sense to
bind states to particular signal values when the implementation is
(partially) known. If the state machine only produces 1s and 0s
as output then a bit vector can be used, but since in some states
outputs may not be driven, and in other states outputs may be
irrelevent, I think Logic is better: 'Z' representing undriven and
'X' indicating that for a particular state the output can be a 1 or
0 (for synthesis) and is unreliable in simulation. I would also like
to be able to use the state variable directly as an output of the state
machine, i.e. the "state" declaration would create a register big
enough to handle the state mapping, which I can use in an "output"
declaration. E.g.:
module FSM(output S, input clk, input reset);
state {S0 = 1'b10, S1 = 1'b0Z, S2 = 1'b1X} S @(posedge clk);
There seems to be an ongoing discusion about the syntax and
semantics of state machine definitions, I would suggest that
wherever possible SystemVerilog syntax and semantics be
defined as a direct mapping to (more verbose) Verilog 2001. I
think that will reduce the amount of work we have to do, and
will make it easier for Verilog 2001 simulator vendors to add
the new functionality (and allow us [end users] to use Verilog 2001
pre-processors as a stop-gap).
Kev.
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