Subject: Re: FSM Section Vote
From: Alec Stanculescu (alec@fintronic.com)
Date: Thu Apr 04 2002 - 11:42:29 PST
Dennis,
Tamio Hoshino, from Applistar, Japan, is interested to follow the
progress we are making on System Verilog (I told him that SystemC is
doomed to oblivion!:-). He is a member of JEIDA, which
participates in the IEEE standardization of Verilog. Tamio will
most likely become one of Japan's representatives to the IEC TC-93
Committee. He was for many years reviewer of papers at DAC, and was
a key contributor to the UDL/I standardization effort.
Due to the time at which our meetings take place it is
difficult for him to attend our phone conferences (they take place
between 1am and 3am his time).
In order to prepare a smooth acceptance of System Verilog in Japan as
well, I propose to put Tamio on our reflector, and provide him with a
draft of the proposed LRM. As he probably cannot attend sufficient
meetings he will not have voting rights. This way he could act as a
lieson to JEIDA and make presentations about our activities in Japan.
Please let me know what I should tell him.
Best regards,
Alec Stanculescu
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