Subject: RE: FSM Section Vote
From: Dennis Brophy (dennisb@model.com)
Date: Thu Apr 04 2002 - 16:48:14 PST
The proposal right now is, as Stu wrote it:
Remove the State Machine Section (section 9 in draft 4) from the
SystemVerilog 3.0 LRM, and defer transition statement and operators for
consideration in SystemVerilog 3.1.
VOTE: NO
On Stu's second proposal to remove the state keyword, as we did not decide
to do an email vote on this in the meeting although it came up, and as it
was only briefly discussed at the end of the meeting when some people had
left, I would like to NOT have an email vote on this now, but to leave it
to a vote during the next meeting. I think that there are folks who would
like to make some points on this before a vote is taken.
VOTE: OK, there's no vote on this, right?
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