25th Verilog++ Meeting Minutes 4/29/02


Subject: 25th Verilog++ Meeting Minutes 4/29/02
From: Dave Kelf (davek@co-design.com)
Date: Mon Apr 29 2002 - 10:30:53 PDT


25th Verilog++ Committee Meeting Minutes
April 29th, 2002
Vassilios leading, Davek taking minutes

ATTENDANCE
(aaaaaaaaaaaaaa-aaaaaaaaaa) Vassilios Gerousis *
(aaaaa-aaaraaa-aaarar-aaaa) Dave Kelf *
(---------------aaa--aaaa=) John Sanguinetti
(aaaaaaaaaaaaaaaa--a-aa---) Dennis Brophy *
(aaaaaaa-aaaaaaaaaaaaaaaaa) Stu Sutherland *
(a---------a--------aaaaa=) David Knapp *
(aaaaaaaaa--aaaaaraaar-aaa) Tom Fitzpatrick *
(---------a-arraa-aaaaaaa=) Phil Moorby
(aaaaaaa-aaa-aaaa-aaaaaaaa) Anders Nordstrom *
(aaaaaa--aaaaaa--a-aaaaaaa) Cliff Cummings *
(aaaa--aaaaaaaaraaa-aaaaaa) Simon Davidmann *
(aaaaaaaaaaaaaaaaaaaaa====) Peter Flake *
(aaaaaa-a--aaaa-aaaaa-aaaa) Stefen Boyd *
(aaaaa---aaaaaaaaaaaaaaaaa) David Smith *
(aaaa-aa-aaa-aaa--a-a--aa=) Mike McNamara *
(aaaaaaaaaaaaaaaaaa=======) Kevin Cameron *
(aaaaa-aaaaa-a-aa-a=======) Andy Tsay *
(a-aaaaaaaa-aa============) Alec Stanculescu *
(a-aa-aa----a=============) Adam Krolnik *
(aa-aaaa-aaa==============) Paul Graham *
(----------a==============) David Seifert
(------a==================) Alex Zamfirescu
(a========================) Jayant Nagda *
(-========================) Karen Pieper
(a========================) Erich Marschner *
(a========================) Prakash Narian *

AGENDA
1- Introduction of new members.
2- Review the document (Draft 7):
      a- The new members can help us by reading and identifying areas for
clarification.
      b- Wording mistakes, model errors, typographical errors, grammatical
errors, etc.
3- Voting.
4- SystemVerilog 3.1 topics (if we have time).

MINUTES
Introduction to new members
Erich Marschner
Jayant Nagda
Prakash Narian

LRM Draft 7 Review
Draft 7 - no issues from Stu to report.
Two questions in previous email sent with Draft 7.
a. Peter F already asked one about casting
b. Add assertions BNF into section using existing style. Not into main BNF
Written substantial part of Glossary - will send to PeterF tomorrow for
review and completion.
ACTION Stu/Peter: Complete Glossary

Alec: BNF written incorrectly in that it cannot be used for automated
syntax checking. Peter - consider intention - meant to enable human
understanding - not necessarily for use with YACC, etc. Mac/Alec agreed.
Alec - can't run it through internal tool to verify. Stefen - more time
needed. No action required for now. Need to look at for 3.1. Alec will make
changes to make it work and note them - for 3.1.
ACTION Stu: Note required in manual to indicate that BNF may have
ambiguities and reference should be made to the text of the LRM.

Adam: Asked about assertion BNF - suggested that a delay, event, or repeat
had to be present before a statement. Based on BNF A.6.10. Looks OK,
explanation included in section 11.4. No action required.

LRM Acceptance Vote
Vote on proposal to accept current LRM by the committee and submit it to
the Accellera board for standardization.
Votes from eligible members
Vassilios Gerousis chair vote if required
Dave Kelf for
Dennis Brophy for
Stu Sutherland for
Tom Fitzpatrick for
Anders Nordstrom for
Cliff Cummings for
Simon Davidmann for
Peter Flake for
Stefen Boyd not present - email vote requested
David Smith for
Mike McNamara for
Kevin Cameron against
Andy Tsay for
Alec Stanculescu for
Adam Krolnik for
Paul Graham for

Voting draft should be called Draft 8 - and should be available from Stu on
Wednesday.
Please can everyone review this draft and email back to Stu any final comments.

FUTURE MEETINGS
Meeting next week to discuss 3.1 issues and to perform a final, clean-up
review of the 3.1 document.
May 6th, 9:00am PST, 12:00pm EDT, 5:00pm BST, 6:00pm Central Euro.
Call In 405 244 5555 access code 3715

Face to face meeting to be held the week before DAC
Wednesday June 5th, Mentor Graphics in Bay Area.

Thanks Everyone.
______________________________

Dave Kelf
VP Marketing
Co-Design Automation, Inc.

Tel: 1 877 6 CODESIGN ext 404
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Email: davek@co-design.com
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"Faster, Smarter Verilog"
______________________________



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