Subject: SystemVerilog Typos
From: Dennis Brophy (dennisb@model.com)
Date: Mon Apr 29 2002 - 10:06:02 PDT
Stu,
Here are the typos I've seen from my last review of the document (version
7).
p. 18: The last sentence before section before 5.4 has some bolded items
where the font is not correct.
p. 30: an input is named enable in an example to explain iff, but the prose
to explain the example refers to rst == 0, is that incorrect? Should it
have been enable == 0?
p. 39: At the bottom of the page, should change "SystemVerilog,," to
"SystemVerilog,"
p. 50: In 12.2, "elaboration.." should be changed to "elaboration."
p. 53: At top of page the sentence "A module declaration may appear after is
instantiated in.." should be changed to "A module declaration may appear
after it is instantiated in..."
p. 63: At the bottom of the page, "modelled" should be changed to "modeled".
p. 124: Should the entry in the P section called "port connections..*"
remain that way?
-Dennis
-- Dennis Brophy Email: dennisb@model.com Director of Strategic Business Development Phone: +1 503-526-1694 Model Technology Inc. Fax: +1 503-526-5465 10450 SW Nimbus Ave, Suite R Mobile: +1 503-706-8987 Portland, OR 97223-4347 Home Fax: +1 503-579-2664
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