Subject: Re: SystemVerilog 21st Meeting Minutes 4/1/02
From: Adam Krolnik (krolnik@lsil.com)
Date: Mon Apr 08 2002 - 08:43:24 PDT
Hi Peter;
I don't remember any explanation of how one explicitly instantiates
something in $root. Is it just instantiating a module outside
of a module definition
>The order of elaboration we use is as follows:
>Look for explicit instantiation in $root.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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