Re: SystemVerilog 21st Meeting Minutes 4/1/02

Subject: Re: SystemVerilog 21st Meeting Minutes 4/1/02
From: Peter Flake (flake@co-design.com)
Date: Mon Apr 08 2002 - 06:48:48 PDT

Dave,

Here are my actions:

At 05:34 PM 4/1/02 -0500, Dave Kelf wrote:
Section 7.9 - ACTION Peter needs to get back to Committee on rules for unspecified size in concatenation

Currently SUPERLOG allows literals of unspecified size in concatenation.  If the committee wishes to follow the existing rules, this could be made an error (semantic not syntactic) in SystemVerilog.

Section 10 Note 2 - ACTION Peter to look at 10.6 / 10.7 and send clean up suggestions in email

I suggest removing section 10.6 completely, since it does not describe any new functionality in SystemVerilog.

Section 11/12 - ACTION Please everyone review and make sure these sections are OK
Section 12.2 - ACTION Peter to analyze and get back to Stu

The order of elaboration we use is as follows:
Look for explicit instantiation in $root. 
If none, look for implicit instantiations (i.e. uninstantiated modules).
Traverse non-generate instantiations depth-first in source order.
Then execute generate blocks depth-first in source order.

Alternatively the second paragraph of 12.2 could be deleted.

Section 12.4 - Extern proposal needs to be deferred for 3.1. ACTION Kevin to provide proposal.
Section 12.5 Note 1 - Change to: including packed array, structure, and union.
Section 12.5 Note 2 - Need to spell out for cases of port specification, and the resulting action
For the first port, if neither type nor direction is specified, it is assumed to be a member of a port list, i.e. Verilog 95 syntax. If the port type but no direction is specified, the port direction defaults to inout.  If the port direction but no type is specified, the port type defaults to wire.

For a subsequent port, if the type and direction are omitted, they are inherited from the previous port.  If only the direction is omitted, it is inherited from the previous port.  If only the type is omitted, it defaults to wire.

ACTION on Peter to provide documentation for 6 to cover $left / $right.


The current Co-Design implementation of $left is that it has a single argument, the array name, and returns the left bound of the most significant dimension.  Similarly $right returns the right bound.  These can be applied to a slice to find the next dimension, etc.  Paul's proposal extends them to have a dimension number, with 1 the most significant ( slowest varying ) dimension.

I prefer $length (like VHDL) to $size for the number of elements in the dimension.

Peter.

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