Subject: RE: Port Connection Rules
From: David Smith (david_smith@avanticorp.com)
Date: Wed Aug 22 2001 - 16:06:27 PDT
Got it. Sounds like a warning about multiple out connections on a variable through ports would be a useful implementation.
David
-----Original Message-----
From: Stefen Boyd [mailto:stefen@boyd.com]
Sent: Wednesday, August 22, 2001 3:51 PM
To: David Smith
Cc: 'vlog-pp@eda.org'
Subject: Re: Port Connection Rules
Hi David,
At 03:29 PM 8/22/2001 -0700, David Smith wrote:
>1. Where is the "shared variable behavior" defined and how does it interact with the simulation cycle?
The shared variable behavior is what we
were talking about with the logic type.
It's like port collapsing... the ports
don't behave the way they do with current
verilog (i.e. every time you pass through
a port it's like doing a continuous
assignment).
>2. Does this really make sense? Would it not be better to limit the output to single drivers on a variable?
Because of #1, assignments to a shared variable
from different modules is the same as writing
to it from multiple procedural blocks in a
single module. I can't say it's advisable, but
having these data types shared simplifies the
problem of port propagation by removing the
ports from the problem.
Regards,
Stefen
--------------------
Stefen Boyd Boyd Technology, Inc.
stefen@BoydTechInc.com (408)739-BOYD
www.BoydTechInc.com (408)739-1402 (fax)
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