Subject: Port Connection Rules
From: David Smith (david_smith@avanticorp.com)
Date: Wed Aug 22 2001 - 15:29:30 PDT
Greetings,
In thinking some more about the "Port Connection Rules" on page 50 of the Superlog document I am bothered by the following:
For port declaration of variable type:
"An output can be connected to a variable (or a concatentation) of a compatible data type, and has shared variable behavior if multiple outputs are connected (last write wins)."
Two questions:
1. Where is the "shared variable behavior" defined and how does it interact with the simulation cycle?
2. Does this really make sense? Would it not be better to limit the output to single drivers on a variable?
This has again come up by trying to reconcile the Verilog-AMS wreal declaration with the real declaration in VerilogPP.
Regards
David
David W. Smith
Architect
> Avant! Corporation
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